1. Field of the Invention
The present invention relates to a semiconductor device using a crystalline semiconductor film that contains silicon and to a method of manufacturing the semiconductor device. Specifically, the present invention relates to a semiconductor device having an n-channel thin film transistor (hereinafter referred to as TFT) formed from a crystalline semiconductor film that contains silicon and to a method of manufacturing the semiconductor device.
2. Description of the Related Art
In recent years, the technique of making a semiconductor circuit from TFTs formed on an insulating substrate such as a glass substrate has rapidly progressed and is utilized to manufacture active matrix liquid crystal display devices and other electrooptical devices. An active matrix liquid crystal display device is a monolithic liquid crystal display device in which a pixel matrix circuit and a driver circuit are placed on the same substrate. The above technique is also utilized to develop a system on panel incorporating logic circuits such as a γ correction circuit, a memory circuit, and a clock generating circuit.
Driver circuits and logic circuits as above need to operate at high speed. Therefore, it is inappropriate to use an amorphous silicon film for the semiconductor layer that serves as an active layer of a TFT of these circuits. TFTs whose active layers are polycrystalline silicon films are thus becoming the mainstream. There is a need for a glass substrate as a substrate on which TFTs are formed because of its inexpensiveness, and a low temperature process applicable to a glass substrate is actively being developed.
One of the low temperature process techniques that have been developed is a technique for forming a crystalline silicon film on a glass substrate, which is disclosed in Japanese Patent Application Laid-open No. Hei 7-130652. According to the technique described in the publication, an amorphous silicon film is provided with a catalytic element that accelerates crystallization and the amorphous silicon film is then crystallized by heat treatment. This crystallization technique makes it possible to lower the temperature at which an amorphous silicon film is crystallized and shorten the crystallization time. The technique allows a glass substrate with a low heat resistance to have a large area crystalline silicon film on its surface, opening the gate to employment of glass substrate of crystalline silicon film in TFTs.
This technique of crystallizing an amorphous silicon film uses as the catalytic element Ni (nickel), Co (cobalt), or the like. Therefore, when used in a TFT, a crystalline silicon film obtained by this crystallization technique can affect electric characteristics and reliability of the TFT. In fact, it has been confirmed that the catalytic element remaining in the crystalline silicon film segregates irregularly in a grain boundary and that the grain boundary region in which the catalytic element segregates serves as a leak path of a weak current to cause an eruptive increase in OFF current in the TFT. Then, a technique of gettering a catalytic element by a halogen element has been developed (See Japanese Patent Application Laid-open No. Hei 10-125926). This gettering technique requires high temperature heat treatment at 800° C. or higher and is not applicable to a glass substrate having a low heat resistance. Although the technique is capable of lowering the crystallization temperature for obtaining a crystalline silicon film than the heat resistance temperature of a glass substrate, the temperature during gettering of catalytic element by the technique is no lower than 800° C. to make it practically impossible to apply the low temperature process using a catalytic element to a glass substrate.
Against this background, a highly efficient catalytic element gettering technique has been developed and disclosed in Japanese Patent Application Laid-open No. Hei 11-054760. According to the technique described in the publication, catalytic elements in a gettering subject region (a region that is not doped with a Group 13 element and a Group 15 element) are thermally diffused and moved to a gettering region, and the catalytic elements are then gettered in the gettering region by a Group 13 element (typically boron (B)) and a Group 15 element (typically, phosphorus (P)). This technique consists of the following three steps.
The first step is to obtain a crystalline silicon film by crystallizing an amorphous silicon film using a catalytic element. The second step is to form a gettering region by selectively doping the crystalline silicon film with a Group 13 element (typically B) and a Group 15 element (typically P). The third step is to move catalytic elements in a gettering subject region to a gettering region through thermal diffusion induced by heat treatment for gettering.
In applying the above gettering technique to a process of manufacturing a TFT, there are three major application modes given below.
According to Application Mode 1, a gettering subject region is a region including a semiconductor layer formed from a crystalline silicon film and composed of a source region, drain region, and channel region of a TFT. A region in the periphery of the gettering subject region is selectively doped with both a Group 13 element (typically B) that imparts the p-type conductivity and a Group 15 element (typically P) that imparts the n-type conductivity, thereby forming a gettering region. Then, heat treatment is conducted for gettering.
According to Application Mode 2, the entire region of a crystalline silicon film except a channel region is a gettering region. In other words, a source region and a drain region, and regions other than a semiconductor layer make the gettering region. Specifically, this application mode is comprised of: a step of forming a resist mask on a region that serves as the channel region of the TFT after the crystalline silicon film is formed using a catalytic element (before the semiconductor layer is formed); a doping step using both a Group 13 element (typically B) that imparts the p-type conductivity and a Group 15 element (typically P) that imparts the n-type conductivity; a step of removing the resist mask; and a gettering step for gettering the catalytic element from the region serving as the channel region through heat treatment. Since the gettering region includes a part of the source region and drain region, Application Mode 2 can have a larger gettering region as compared to Application Mode 1.
According to Application Mode 3, a channel region in a semiconductor layer that is formed from a crystalline silicon film is a gettering subject region whereas a source region and a drain region in the semiconductor layer alone make a gettering region. Impurity elements in the source region and drain region double as gettering sources. Specifically, this application mode is comprised of: a step of forming the semiconductor layer after the crystalline silicon film is formed using a catalytic element; a step of forming a gate electrode; a step of doping the semiconductor layer with a Group 13 element (typically B) that imparts the p-type conductivity and a Group 15 element (typically P) that imparts the n-type conductivity while using the gate electrode as a mask to form the source region and the drain region; and a step of thermally activating impurity elements in the source region and drain region and simultaneously gettering the catalytic element in the channel region through heat treatment. Since the gettering region is confined to the semiconductor layer and is smaller in surface area as compared to Application Mode 2, Application Mode 3 is that much less effective in gettering the catalytic element in the channel region. On the other hand, Application Mode 3 integrates the step of introducing a gettering source for forming a gettering region with the impurity doping step for forming a source region and a drain region and is therefore advantageous in improving throughput.
Application Mode 3 improves the degree of integration of TFT as well as throughput and is therefore convenient and useful. However, when Application Mode 3 is employed in manufacture of an n-channel TFT and a p-channel TFT, the catalytic element gettering efficiency in a channel region is lower in the n-channel TFT than in the p-channel TFT. The problem of Application Mode 3 regarding the low gettering efficiency of the n-channel TFT will be described in detail below.
Semiconductor layers of the n-channel TFT and p-channel TFT are doped with an n-type impurity element that imparts the n-type conductivity while using gate electrodes as masks. Thereafter, the semiconductor layer of the p-channel TFT alone is doped with a p-type impurity element that imparts the p-type conductivity in an amount large enough to convert the layer's conductivity while using the gate electrode as a mask. Thus formed are source regions and drain regions of the n-channel TFT and p-channel TFT. The source region and drain region of the p-channel TFT therefore contain an element that imparts the n-type conductivity and an element that imparts the p-type conductivity with the amount of p-type impurity exceeding the amount of n-type impurity. On the other hand, the source region and drain region of the n-channel TFT contain only an element that imparts the n-type conductivity. During the gettering treatment that doubles as impurity ion activation treatment, the catalytic element in the channel region of the p-channel TFT is gettered by the element that imparts the n-type conductivity and the element that imparts the p-type conductivity and is contained in an amount exceeding the amount of n-type impurity. The catalytic element in the n-channel TFT, on the other hand, is gettered solely by the element that imparts the n-type conductivity.
It has been confirmed that the gettering efficiency is higher when an element that imparts the n-type conductivity and an element that imparts the p-type conductivity and is contained in a concentration exceeding the concentration of n-type impurity both participate in gettering than when the gettering source consists solely of the element that imparts the n-type conductivity (See Japanese Patent Application Laid-open No. Hei 11-054760). In other words, an n-channel TFT with the gettering source consisting of the element that imparts the n-type conductivity alone is inferior to a p-channel TFT in terms of efficiency in gettering catalytic element of its channel region.
When the effect of gettering catalytic element in a channel region is lower in an n-channel TFT than in a p-channel TFT, gettering in the n-channel TFT could be insufficient and it may be necessary to change gettering treatment conditions so as to avoid insufficient gettering. Therefore, it can be said that the problem regarding gettering efficiency of an n-channel TFT is accompanied with a process margin problem of gettering treatment.